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发表于 2006-11-19 02:16 · 北京
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下面是引用eos于2006-11-19 02:06发表的:
PS3的CELL和服务器用的不一样,PS3应该有改动(个人认为是简化版CELL)
这个不知道耶。
IBM Cell 服务器上用的Cell的内存控制器是这样的。
1.2.3 Memory Interface Controller
The on-chip Memory Interface Controller (MIC) provides the interface between the EIB and physical
memory. It supports one or two Rambus Extreme Data Rate (XDR) memory interfaces, which
together support between 64 MB and 64 GB of XDR DRAM memory.
Memory accesses on each interface are 1 to 8, 16, 32, 64, or 128 bytes, with coherent memoryordering.
Up to 64 reads and 64 writes can be queued. The resource-allocation token manager
provides feedback about queue levels.
The MIC has multiple software-controlled modes, including fast-path mode (for improved latency
when command queues are empty), high-priority read (for prioritizing SPE reads in front of all
other reads), early read (for starting a read before a previous write completes), speculative read,
and slow mode (for power management). The MIC implements a closed-page controller (bank
rows are closed after being read, written, or refreshed), memory initialization, and memory scrubbing.
The XDR DRAM memory is ECC-protected, with multi-bit error detection and optional single-bit
error correction. It also supports write-masking, initial and periodic timing calibration, dynamic
width control, sub-page activation, dynamic clock gating, and 4, 8, or 16 banks. |
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